1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory system and, more particularly, to a nonvolatile semiconductor memory system having a nonvolatile memory cell array which is divided into erase blocks.
2. Description of Related Art
In a conventional nonvolatile semiconductor memory device having memory cells each including a floating gate and a control gate, a phenomenon called "drain disturbance" poses a serious problem. Drain disturbance is an unintentional gradual loss or disappearance of data programmed into the memory cell floating gate caused by a tunneling current between the drain electrode and the floating gate due to a high electrical field between the drain electrode and the floating gate.
For example, assume two floating-gate type memory cell transistors have their drain electrodes connected via a bit line. To program data to the first memory cell transistor, a high voltage of about 10V is applied to the control gate electrode of the first memory cell transistor and a voltage of about 5V is applied to the drain electrode of the first memory cell transistor. This condition is maintained for a relatively long period of time, for example 10 .mu.s, causing hot electrons to be charged into the floating gate of the first memory cell transistor. During this programming of the first memory cell transistor, the control gate electrode of the second memory cell transistor is applied with 0V, and the drain electrode of the second memory cell transistor is applied with 5V via the bit line. A drain stress due to the potential difference between the drain electrode and the floating gate of the second memory cell transistor causes a tunneling current between the drain electrode and the floating gate of the second memory cell transistor. Such tunneling current causes disappearance of data programmed into the floating gate of the second memory cell transistor. This is drain disturbance. Drain disturbance poses a serious problem when a great number of memory cell transistors are connected via a common bit line because the duration of time that a single memory cell suffers from drain stress is multiplied by the number of memory cell transistors sharing the common bit line.
Typically, the problems of drain disturbance in memory devices are overcome by optimization of cell design. However, some nonvolatile semiconductor memory devices include memory cell arrays which are divided into erase blocks (see, for example, "Symposium on VLSI Technology," pp. 77-78, 1991). In such memories, memory cells in one erase block are programmed/erased independently from memory cells in other erase blocks. Thus, the duration of drain stress to one particular memory cell may be extremely long. This drain stress becomes most severe when the data of the memory cells in one erase block is not updated and the data of the memory cells in other erase blocks is frequently programmed and erased. In this case, the duration of drain stress one memory cell may suffer is further multiplied by the number of programming/erasing cycles specified by the manufacturer, for example 100,000. Thus, drain disturbance in a nonvolatile memory device having a memory cell array divided into erase blocks poses a serious problem that has not yet been overcome by optimization of cell design.